System-on-chip including a power path controller and electronic device

ABSTRACT

A system on chip (SoC) includes a plurality of function circuits including a plurality of logic circuits and a plurality of function circuits each of which includes a logic circuit and a memory, and a plurality of power path controllers respectively coupled to a plurality of first power sources at first input terminals, commonly coupled to a second power source at second input terminals, and respectively coupled to the memories at output terminals. The logic circuits are respectively coupled to the first power sources, and configured to be supplied with a plurality of first power supply voltages from the first power sources, respectively. Each of the memories is configured to be selectively supplied, by a corresponding one of the power path controllers, with one of a corresponding one of the first power supply voltages from a corresponding one of the first power sources and a second power supply voltage from the second power source.

CROSS-REFERENCE TO THE RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2014-0141682, filed on Oct. 20, 2014, in the Korean IntellectualProperty Office (KIPO), the disclosure of which is incorporated byreference in its entirety herein.

BACKGROUND

1. Technical Field

Example embodiments relate generally to semiconductor devices, and moreparticularly to a system-on-chip (SoC) including a power path controllerand an electronic device including the SOC.

2. Discussion of the Related Art

A system-on-chip (SoC) generally refers to a processing system thatintegrates various functional circuits (e.g., a central processing unit,a memory, an interface unit, a digital signal processing unit, an analogsignal processing unit, etc.) in a single or a few semiconductorintegrated circuits (ICs) to implement an electronic system, such as acomputer system, using a limited number of ICs. Recently, SoCs haveevolved to complex systems including various functions such asmultimedia, graphics, interfaces, security functionality, etc. Asdiverse capabilities and functionality converge in portable devices thatare battery-powered, efforts are ongoing to reduce power consumption insuch portable devices while enhancing the performance thereof.

SUMMARY

At least one example embodiment of the inventive concept provides asystem-on-chip (SoC) including a power path controller.

At least one example embodiment of the inventive concept provides anelectronic device including the SoC.

According to example embodiments, there is provided an SoC which mayinclude a plurality of function circuits each of which includes a logiccircuit and a memory, and a plurality of power path controllersrespectively coupled to a plurality of first power sources at firstinput terminals, commonly coupled to a second power source at secondinput terminals, and respectively coupled to the memories at outputterminals. The logic circuits may be respectively coupled to the firstpower sources, and configured to be supplied with a plurality of firstpower supply voltages from the first power sources, respectively. Eachof the memories may be configured to be selectively supplied, by acorresponding one of the power path controllers, with one of acorresponding one of the first power supply voltages from acorresponding one of the first power sources and a second power supplyvoltage from the second power source.

Each of the first power supply voltages may be a power supply voltagewhich is dynamically changed according to an operating condition of acorresponding one of the function circuits, and the second power supplyvoltage may be a fixed power supply voltage.

The second power supply voltage may have a voltage level the same as avoltage level of a minimum power supply voltage required by the memorycores.

The second power supply voltage may have a voltage level higher than avoltage level of a minimum power supply voltage required by the memorycores.

The power path controllers may be respectively coupled to the firstpower sources through a plurality of first power supply lines, and maybe commonly coupled to the second power source through a single secondpower supply line.

Each power path controller may be configured to transfer thecorresponding one of the first power supply voltages from thecorresponding one of the first power sources to a corresponding one ofthe memories in response to the corresponding one of the first powersupply voltages having a voltage level higher than a voltage level ofthe second power supply voltage, and transfer the second power supplyvoltage from the second power source to the corresponding one of thememories in response to the corresponding one of the first power supplyvoltages having a voltage level lower than the voltage level of thesecond power supply voltage.

Each power path controller may include a first switch located betweenthe corresponding one of the first power sources and the correspondingone of the memories, a second switch located between the second powersource and the corresponding one of the memories, a comparatorconfigured to compare the corresponding one of the first power supplyvoltages from the corresponding one of the first power sources with thesecond power supply voltage from the second power source, and a switchcontroller configured to activate the first switch in response to thecorresponding one of the first power supply voltages having the voltagelevel higher than the voltage level of the second power supply voltage,and activate the second switch in response to the corresponding one ofthe first power supply voltages having the voltage level lower than thevoltage level of the second power supply voltage.

The first power supply voltage supplied from one of the first powersources may be a fixed power supply voltage, and the first power supplyvoltages supplied from the others of the first power sources may bepower supply voltages which are dynamically changed according tooperating conditions of corresponding ones of the function circuits. Thesecond input terminals of the power path controllers may be commonlycoupled to, as the second power source, the one of the first powersources supplying the fixed power supply voltage.

The first power sources may be buck converters, and the second powersource may be a low dropout regulator.

The first power sources and the second power source may be included in apower management integrated circuit.

The second power source may be located inside the SoC.

According to example embodiments, the SoC may further include anotherfunction circuit comprising a logic circuit and a memory which areconfigured to be supplied with the second power voltage from the secondpower source.

Each of the first power supply voltages may be a power supply voltagewhich is dynamically changed according to an operating condition of acorresponding one of the function circuits.

Each of the first power supply voltages may be a power supply voltagewhich is dynamically changed according to an operating condition of acorresponding one of the function circuits, and the second power supplyvoltage may be dynamically changed according to an operating conditionof the other function circuit while the second power supply voltage hasa voltage level higher than or equal to a voltage level of a minimumpower supply voltage required by the memories respectively included inthe function circuits and the memory included in the other functioncircuit.

The second power source may be included in the SoC, and may generate afixed power supply voltage as the second power supply voltage.

According to example embodiments, there is provided an electronic devicewhich may include the above SoC and a power management integratedcircuit which is connected to the SoC. The power management integratedcircuit may include the plurality of first power sources configured togenerate the first power supply voltages each of which is dynamicallychanged according to an operating condition of a corresponding one ofthe function circuits, and the second power source configured togenerate a fixed second power supply voltage.

According to example embodiments, there is provided an SoC which mayinclude a plurality of first function circuits belonging to a firstpower group, each of the first function circuits including a first logiccircuit and a first memory, a plurality of second function circuitsbelonging to a second power group, each of the second function circuitsincluding a second logic circuit and a second memory, a plurality offirst power path controllers respectively coupled to a plurality offirst power sources at first input terminals, commonly coupled to asecond power source at second input terminals, and respectively coupledto the first memories at output terminals, and a plurality of secondpower path controllers respectively coupled to a plurality of thirdpower sources at first input terminals, commonly coupled to a fourthpower source at second input terminals, and respectively coupled to thesecond memories at output terminals, wherein the first logic circuitsare respectively coupled to the first power sources, and are configuredto be supplied with a plurality of first power supply voltages from thefirst power sources, respectively. The second logic circuits may berespectively coupled to the third power sources, and configured to besupplied with a plurality of third power supply voltages from the thirdpower sources, respectively. Each of the first memories may beconfigured to be selectively supplied, by a corresponding one of thefirst power path controllers, with one of a corresponding one of thefirst power supply voltages from a corresponding one of the first powersources and a second power supply voltage from the second power source.Each of the second memories may be configured to be selectivelysupplied, by a corresponding one of the second power path controllers,with one of a corresponding one of the third power supply voltages froma corresponding one of the third power sources and a fourth power supplyvoltage from the fourth power source.

Each of the first power supply voltages may be a power supply voltagewhich is dynamically changed according to an operating condition of acorresponding one of the first function circuits, and the second powersupply voltage may be a power supply voltage fixed to a minimum powersupply voltage required by the first memories. Also, each of the thirdpower supply voltages may be a power supply voltage which is dynamicallychanged according to an operating condition of a corresponding one ofthe second function circuits, and the fourth power supply voltage may bea power supply voltage fixed to a minimum power supply voltage requiredby the second memories.

According to example embodiments, there is provided an SoC which mayinclude a first function circuit including a logic circuit and a firstmemory, and a second function circuit including a second memory. Here,the logic circuit may be configured to be supplied with a first voltagewhich is dynamically changed according to an operating condition of thefirst function circuit, and each of the first and second memories may beconfigured to be selectively supplied with one of the first voltage anda second voltage which is the same as or higher than a minimum voltagerequired by the first and second memories, while the second voltage issupplied from one single power source.

The SoC and the electronic device according to example embodiments mayallow memories to share at least one power source that generates a powersupply voltage corresponding to the minimum power supply voltagerequired by the memories, thereby reducing the number of power supplylines between a power management integrated circuit (PMIC) and the SoCand reducing the number of passive elements and the size of the PMIC.

Furthermore, the SoC and the electronic device according to exampleembodiments may selectively supply each memory with a first power supplyvoltage that is dynamically changed according to an operating conditionof a function circuit or a second power supply voltage that is fixed tothe minimum power supply voltage required by the memory, therebyreducing the power consumption and ensuring the normal operation of thememory.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the inventive concept will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings.

FIG. 1 is a block diagram illustrating a system-on-chip (SoC) accordingto example embodiments.

FIG. 2 is a timing diagram illustrating examples of power supplyvoltages supplied to memory cores illustrated in FIG. 1.

FIG. 3 is a block diagram illustrating an example of a power pathcontroller included in a SoC of FIG. 1.

FIG. 4 is a block diagram illustrating a SoC according to exampleembodiments.

FIG. 5 is a timing diagram illustrating examples of power supplyvoltages supplied to memory cores illustrated in FIG. 4.

FIG. 6 is a timing diagram illustrating other examples of power supplyvoltages supplied to memory cores illustrated in FIG. 4.

FIG. 7 is a block diagram illustrating a SoC according to exampleembodiments.

FIG. 8 is a block diagram illustrating a SoC according to exampleembodiments.

FIG. 9 is a block diagram illustrating a SoC according to exampleembodiments.

FIG. 10 is a block diagram illustrating a mobile device according toexample embodiments.

FIG. 11 is a schematic diagram illustrating an example in which themobile device of FIG. 10 is implemented as a smart-phone.

FIG. 12 is a block diagram illustrating an interface included in amobile device according to example embodiments.

FIG. 13 is a block diagram illustrating an electronic device accordingto example embodiments.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Various example embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which some exampleembodiments are shown. The present inventive concept may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present inventiveconcept to those skilled in the art. In the drawings, the sizes andrelative sizes of layers and regions may be exaggerated for clarity.Like numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are used to distinguish oneelement from another. Thus, a first element discussed below could betermed a second element without departing from the teachings of thepresent inventive concept. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of thepresent inventive concept. As used herein, the singular forms “a,” “an”and “the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a block diagram illustrating a system-on-chip (SoC) accordingto example embodiments, FIG. 2 is a timing diagram illustrating examplesof power supply voltages supplied to memory cores illustrated in FIG. 1,and FIG. 3 is a block diagram illustrating an example of a power pathcontroller included in a SoC of FIG. 1.

Referring to FIG. 1, a system-on-chip (SoC) 100 includes a plurality offunction circuits IP1, IP2 and IPN, and a plurality of power pathcontrollers (PPCs) 122, 124 and 126. For example, the SoC 100 may be anapplication processor (AP) included in an electronic device such as amobile device.

The function circuits IP1, IP2 and IPN may be circuits or intellectualproperties (IPs) performing various functions. For example, the functioncircuits IP1, IP2 and IPN may include a central processing unit (CPU), agraphic processing unit (GPU), a bus system, an image signal processor(ISP), a multi-format codec (MFC) block, a file system (FSYS) block, amemory controller (MC), or the like. In some example embodiments, thefunction circuits IP1, IP2 and IPN may belong to different power domainsPD1, PD2 and PDN, or at least one of the function circuits IP1, IP2 andIPN may belong to one same power domain among PD1, PD2 and PDN.

Each function block IP1, IP2 and IPN may include a logic circuit LU1,LU2 and LUN and a memory core MC1, MC2 and MCN, respectively. Here, thememory core MC1, MC2 and MCN may mean a memory cell array including avolatile memory cell that is continuously supplied with a power supplyvoltage to retain stored data, or may collectively mean the memory cellarray, including the volatile memory cell, and at least a portion (e.g.,at least one of a row decoder, a column selector, a write driver or asense amplifier) of a peripheral circuit that performs a write/readoperation for the memory cell array. In some example embodiments, thememory core MC1, MC2 and MCN may be a memory cell array including astatic random access memory (SRAM) cell, or a collection of the memorycell array, including the SRAM cell, and at least a portion of aperipheral circuit for the memory cell array. In other exampleembodiments, the memory core MC1, MC2 and MCN may be a memory cell arrayincluding a dynamic random access memory (DRAM) cell, or a collection ofthe memory cell array, including the DRAM cell, and at least a portionof a peripheral circuit for the memory cell array. The logic circuitLU1, LU2 and LUN may perform related operations or processes forfunctions of each function circuit IP1, IP2 and IPN. Each logic circuitLU1, LU2 and LUN may include at least a portion (e.g., at least one ofthe row decoder, the column selector, the write driver or the senseamplifier) or all of the peripheral circuit for the memory cell array.

In some example embodiments, the logic circuits LU1, LU2 and LUNincluded in the function circuits IP1, IP2 and IPN, or the peripheralcircuits included in the logic circuits LU1, LU2 and LUN may be suppliedwith power from a plurality of first power sources 182, 184 and 186included in a power management integrated circuit (PMIC) 160,respectively. The logic circuits LU1, LU2 and LUN (or the peripheralcircuits included in the logic circuits LU1, LU2 and LUN) may berespectively coupled to the first power sources 182, 184 and 186, andmay respectively receive a plurality of first power supply voltagesVDD1-1, VDD1-2 and VDD1-N from the first power sources 182, 184 and 186.

In some example embodiments, each first power source 182, 184 and 186may dynamically change the first power supply voltage VDD1-1, VDD1-2 andVDD1-N according to an operating condition (e.g., a required throughputor a required operating speed) of a corresponding one of the functioncircuit IP1, IP2 and IPN. In some example embodiments, to reduce powerconsumption of the SoC 100, a dynamic voltage frequency scaling (DVFS)technique that dynamically changes a power supply voltage and/or anoperating frequency may be applied to the SoC 100. For example, when alow throughput or a low operating speed is required with respect to afirst function circuit IP1, a first power source 182 that supplies powerto the logic circuit LU1 of the first function circuit IP1 may decreasea voltage level of the first power supply voltage VDD1-1 applied to thelogic circuit LU1 of the first function circuit IP1 to reduce the powerconsumption.

In some cases, the operating conditions of the function circuits IP1,IP2 and IPN may be different from one another, and thus voltage levelsof the first power supply voltages VDD1-1, VDD1-2 and VDD1-N required bythe function circuits IP1, IP2 and IPN may be different from oneanother. In some example embodiments, the function circuits IP1, IP2 andIPN may belong to the different power domains PD1, PD2 and PDN, thefunction circuits IP1, IP2 and IPN may be supplied with the first powersupply voltages VDD1-1, VDD1-2 and VDD1-N from the first power sources182, 184 and 186, respectively, and the respective first power sources182, 184 and 186 may generate the first power supply voltages VDD1-1,VDD1-2 and VDD1-N having voltage levels that are suitable for thecorresponding function circuits IP1, IP2 and IPN. Accordingly, the powerconsumption of the function circuits IP1, IP2 and IPN may be minimized,and thus the power consumption of the SoC 100 may be minimized. In someexample embodiments, each power domain PD1, PD2 and PDN may include oneor more function circuits, and the number of the first power sources182, 184 and 186 included in the PMIC 160 may correspond to the numberof the power domains PD1, PD2 and PDN included in the SoC 100.

In some example embodiments, to have high power efficiency, the firstpower sources 182, 184 and 186 may be implemented with buck converters(BUCK) having high power conversion efficiency. For example, a powersupply voltage from a battery of an electronic device may be convertedinto the first power supply voltages VDD1-1, VDD1-2 and VDD1-N by thebuck converters, and thus the power efficiency of the electronic devicemay be improved. In other example embodiments, each first power source182, 184 and 186 may be implemented with a low dropout (LDO) regulator,or other converters or regulators.

Although the logic circuits LU1, LU2 and LUN (or the peripheral circuitsincluded in the logic circuits LU1, LU2 and LUN) are supplied with thefirst power supply voltages VDD1-1, VDD1-2 and VDD1-N that aredynamically changed to reduce the power consumption of the SoC 100,operation stability of memory cells may not be ensured at a low powersupply voltage since a distribution of characteristics of the memorycells has widened as the semiconductor manufacturing process has beencontinuously developed, and thus the minimum power supply voltage for anormal operation of the memory cores MC1, MC2 and MCN may be higher thanthe minimum power supply voltage for a normal operation of the logiccircuits LU1, LU2 and LUN. Accordingly, a power supply voltage appliedto the memory cores MC1, MC2 and MCN should be higher than or equal tothe minimum power supply voltage for the normal operation of the memorycores MC1, MC2 and MCN. Further, to ensure the operation stability ofeach memory core MC1, MC2 and MCN, it may be desirable that the powersupply voltage applied to each memory core MC1, MC2 and MCN is higherthan or equal to the power supply voltage applied to the correspondingperipheral circuit. Here, if the memory cores MC1, MC2 and MCN havedifferent minimum power supply voltages for respective normaloperations, the minimum power supply voltage for the normal operation ofthe memory cores MC1, MC2 and MCN may refer to the lowest voltage amongthe different minimum power supply voltages.

In some example embodiments, to ensure this operation stability of thememory cores MC1, MC2 and MCN, the SoC 100 may receive a second powersupply voltage VDD2 that is a fixed power supply voltage from at leastone second power source 190 included in the PMIC 160. In some exampleembodiments, the second power supply voltage VDD2 may have a voltagelevel the same as a voltage level of the minimum power supply voltagerequired by the memory cores MC1, MC2 and MCN. In other exampleembodiments, the second power supply voltage VDD2 may have a voltagelevel higher than a voltage level of the minimum power supply voltagerequired by the memory cores MC1, MC2 and MCN. In some exampleembodiments, to generate the second power supply voltage VDD2 that isstable with less noise (e.g., ripple), the second power source 190 maybe implemented with a low dropout (LDO) regulator. Further, in someexample embodiments, to improve the power efficiency, the power supplyvoltage of the battery may be first converted by a buck converter, andthen may be converted again into the second power supply voltage VDD2 bythe LDO regulator. In other example embodiments, the second power source190 may be implemented with the buck converter, or other converters orregulators. Further, the SoC 100 may selectively supply thecorresponding first power supply voltages VDD1-1, VDD1-2 and VDD1-N orthe second power supply voltage VDD2 to the respective memory cores MC1,MC2 and MCN by using the power path controllers 122, 124 and 126.

The power path controllers 122, 124 and 126 may be respectively coupledto the first power sources 182, 184 and 186 at first input terminalsIN1, may be commonly coupled to the second power source 190 at secondinput terminals IN2, and may be respectively coupled to the memory coresMC1, MC2 and MCN at output terminals OUT. Each power path controller122, 124 and 126 may compare a corresponding one of the first powersupply voltages VDD1-1, VDD1-2 and VDD1-N from a corresponding one ofthe first power sources 182, 184 and 186 with the second power supplyvoltage VDD2 from the second power source 190, and may selectivelyprovide the corresponding one of the first power supply voltages VDD1-1,VDD1-2 and VDD1-N or the second power supply voltage VDD2 to acorresponding one of the memory cores MC1, MC2 and MCN according to aresult of the comparison. Thus, while the power supply voltage suitablefor the operating condition of each function circuit IP1, IP2 and IPN issupplied to the corresponding memory core MC1, MC2 and MCN, it may beensured that the power supply voltage supplied to the correspondingmemory core MC1, MC2 and MCN is higher than or equal to the minimumpower supply voltage required by the memory core MC1, MC2 and MCN.

For example, as illustrated in FIG. 2, the first power supply voltagesVDD1-1, VDD1-2 and VDD1-N may be dynamically changed according to theoperating conditions of the corresponding function circuits IP1, IP2 andIPN, and the second power supply voltage VDD2 may be fixed to theminimum power supply voltage required by the memory cores MC1, MC2 andMCN or to a power supply voltage higher than the minimum power supplyvoltage. Each power path controller 122, 124 and 126 may transfer, as anoutput power supply voltage PPC1_OUT, PPC2_OUT and PPCN_OUT, a higherone of the corresponding first power supply voltage VDD1-1, VDD1-2 andVDD1-N and the second power supply voltage VDD2 to the correspondingmemory core MC1, MC2 and MCN. That is, each memory core MC1, MC2 and MCNmay be supplied, by the corresponding power path controller 122, 124 and126, with the higher one of the corresponding first power supply voltageVDD1-1, VDD1-2 and VDD1-N from the corresponding first power source 182,184 and 186 and the second power supply voltage VDD2 from the secondpower source 190. Accordingly, each memory core MC1, MC2 and MCN may besupplied with the power supply voltage higher than or equal to theminimum power supply voltage required by the memory cores MC1, MC2 andMCN, and thus the operation stability of each memory core MC1, MC2 andMCN may be ensured.

Referring to FIG. 3, in some example embodiments, each power pathcontroller 200 may transfer the first power supply voltage VDD1 from thefirst power source 180 to the memory core MC when the first power supplyvoltage VDD1 from the first power source 180 has a voltage level higherthan a voltage level of the second power supply voltage VDD2 from thesecond power source 190, and may transfer the second power supplyvoltage VDD2 from the second power source 190 to the memory core MC whenthe second power supply voltage VDD2 from the second power source 190has a voltage level higher than a voltage level of the first powersupply voltage VDD1 from the first power source 180. To perform thisoperation, each power path controller 200 may include a first switch 250located between the first power source 180 and the memory core MC, asecond switch 270 located between the second power source 190 and thememory core MC, a comparator 210 that compares the first power supplyvoltage VDD1 from the first power source 180 with the second powersupply voltage VDD2 from the second power source 190, and a switchcontroller 230 that selectively actives the first switch 250 or thesecond switch 270 according to a result of the comparison. For example,the switch controller 230 may generate a first switching signal SWS1 toactivate the first switch 250 when the first power supply voltage VDD1is higher than the second power supply voltage VDD2, and may generate asecond switching signal SWS2 to activate the second switch 270 when thesecond power supply voltage VDD2 is higher than the first power supplyvoltage VDD1.

In some example embodiments, each power path controller 200 may furtherinclude a first resistor between the switch controller 230 and the firstswitch 250, and a second resistor between the switch controller 230 andthe second switch 270, thereby preventing voltage/current peaking causedby a sudden switch of power supply paths. In some example embodiments,the first and second switches 250 and 270 may be PMOS transistors, andeach power path controller 200 may further include first PMOStransistors that apply a higher one of a voltage of a source of thefirst switch 250 and a voltage of a drain of the first switch 250 to abody of the first switch 250 in response to the first switching signalSWS1, and second PMOS transistors that apply a higher one of a voltageof a source of the second switch 270 and a voltage of a drain of thesecond switch 270 to a body of the second switch 270 in response to thesecond switching signal SWS2. Accordingly, a current leakage through thebodies of the first and second switches 250 and 270 may be prevented. Insome example embodiments, each power path controller 200 may furtherinclude a low pass filter at each input terminal of the comparator 210,and the comparator 210 may be a hysteresis comparator. Accordingly, anoise of the first and second power supply voltages VDD1 and VDD2 andundesired power path switching or repeated switching caused by a changeof a load current of the memory core MC may be prevented. In someexample embodiments, the switch controller 230 may further receive anexternal control signal, and may operate in response to the externalcontrol signal.

To ensure that power supply voltages higher than or equal to the minimumpower supply voltage required for the normal operation of the memorycores MC1, MC2 and MCN while the power supply voltages corresponding tocurrent operating conditions of the function circuits IP1, IP2 and IPNare supplied to the function circuits IP1, IP2 and IPN, respectively, arelated art SoC are coupled not only to a plurality of first powersources for respectively supplying power to the function circuits IP1,IP2 and IPN but also to a plurality of second power sources forrespectively supplying power to the memory cores MC1, MC2 and MCN, andeach second power source for the related art SoC dynamically changes thepower supply voltage supplied to the corresponding memory core MC1, MC2and MCN according to the operating condition while maintaining the powersupply voltage higher than or equal to the minimum power supply voltage.Accordingly, in the related art SoC, a same number of power sources asthe memory cores MC1, MC2 and MCN are required to supply power to thememory cores MC1, MC2 and MCN, and thus a corresponding number of powersupply lines are required between the memory cores MC1, MC2 and MCN andthe power sources.

However, in the SoC 100 according to the example embodiments, theplurality of power domains PD1, PD2 and PDN may share the second powersource 190 generating the second power supply voltage VDD2 that is afixed power supply voltage corresponding to the minimum power supplyvoltage required by the memory cores MC1, MC2 and MCN. For example, thepower path controllers 122, 124 and 126 may be coupled to the firstpower sources 182, 184 and 186 through a plurality of first power supplylines PL1-1, PL1-2 and PL1-N, respectively, and may be commonly coupledto the second power source 190 through a single second power supply linePL2. Accordingly, in the SoC 100 according to example embodiments, thenumber of the second power source 190 included in the PMIC 160 may bereduced, the number of passive elements (e.g., capacitors) for thesecond power source 190 may be reduced, and the number of the powersupply lines PL1-1, PL1-2, PL1-N and PL2 between the PMIC 160 and theSoC 100 may be reduced.

As described above, in the SoC 100 according to the example embodiments,each power path controller 122, 124 and 126 may compare the first powersupply voltage VDD1-1, VDD1-2 and VDD1-N that is dynamically changedaccording to the operating condition of the corresponding functioncircuit IP1, IP2 and IPN with the second power supply voltage VDD2 thatis the fixed power supply voltage corresponding to the minimum powersupply voltage required by the memory cores MC1, MC2 and MCN, and mayselectively provide the power supply voltage VDD1-1, VDD1-2 and VDD1-Nor the second power supply voltage VDD2 to the corresponding memory coreMC1, MC2 and MCN according to the result of the comparison. Accordingly,the normal operation of the memory cores MC1, MC2 and MCN may be ensuredwhile reducing the power consumption. Further, the SoC 100 according tothe example embodiments may allow the second power source 190 thatgenerates the second power supply voltage VDD2 to be shared by theplurality of power domains PD1, PD2 and PDN or the plurality of functioncircuits IP1, IP2 and IPN, thereby reducing the number of the secondpower source 190 in the PMIC 160, the number of the passive elements andthe number of the power supply lines PL1-1, PL1-2, PL1-N and PL2 betweenthe PMIC 160 and the SoC 100.

FIG. 4 is a block diagram illustrating a SoC according to exampleembodiments, FIG. 5 is a timing diagram illustrating examples of powersupply voltages supplied to memory cores illustrated in FIG. 4, and FIG.6 is a timing diagram illustrating other examples of power supplyvoltages supplied to memory cores illustrated in FIG. 4.

Referring to FIG. 4, a SoC 300 includes a plurality of function circuitsIP1, IP2 and IPN, and at least one power path controller 324 and 326.The SoC 300 of FIG. 4 may have a similar configuration to a SoC 100 ofFIG. 1, except that one power source 382 of a plurality of power sources382, 384 and 386 that are respectively coupled to the function circuitsIP1, IP2 and IPN is shared instead of a second power source 190illustrated in FIG. 1.

The function circuits IP1, IP2 and IPN may be coupled to the powersources 382, 384 and 386 included in a PMIC 360, respectively. Aplurality of logic circuits LU1, LU2 and LUN respectively included inthe function circuits IP1, IP2 and IPN (or peripheral circuits includedin the logic circuits LU1, LU2 and LUN) may be supplied with a pluralityof power supply voltages VDD1-1, VDD1-2 and VDD1-N from the powersources 382, 384 and 386, respectively.

In some example embodiments, the one power source 382 of the powersources 382, 384 and 386 may supply a fixed power supply voltage VDD1-1,and the other power sources 384 and 386 of the power sources 382, 384and 386 may supply power supply voltages VDD1-2 and VDD1-N that aredynamically changed according to operating conditions of thecorresponding function circuits IP2 and IPN. For example, the fixedpower supply voltage VDD1-1 supplied by the one power source 382 mayhave a voltage level the same as a voltage level of a minimum powersupply voltage required by memory cores MC1, MC2 and MCN, or may have avoltage level higher than the voltage level of the minimum power supplyvoltage. According to example embodiments, each of the one power source382 supplying the fixed power supply voltage VDD1-1 and the other powersources 384 and 386 supplying the dynamically changed power supplyvoltages VDD1-2 and VDD1-N may be implemented with a buck converter, anLDO regulator, or the like.

The memory core MC1 included in the function circuit IP1 correspondingto the one power source 382 supplying the fixed power supply voltageVDD1-1 may directly receive the fixed power supply voltage VDD1-1 fromthe one power source 382, and the memory cores MC2 and MCN included inthe function circuits IP2 and IPN corresponding to the other powersource 384 and 386 supplying the dynamically changed power supplyvoltages VDD1-2 and VDD1-N may be selectively supplied with thedynamically changed power supply voltages VDD1-2 and VDD1-N,respectively, or the fixed power supply voltage VDD1-1 by the power pathcontrollers 324 and 326.

For example, as illustrated in FIG. 5, the one power source 382 maygenerate the fixed power supply voltage VDD1-1 having a voltage levelthe same as or higher than the voltage level of the minimum power supplyvoltage required by the memory cores MC1, MC2 and MCN, and the memorycore MC1 included in the function circuit IP1 corresponding to the onepower source 382 may directly receive the fixed power supply voltageVDD1-1 from the one power source 382. The power path controllers 324 and326 may be commonly coupled to the one power source 382 at second inputterminals 1N2 to receive the fixed power supply voltage VDD1-1, and maybe respectively coupled to the other power sources 384 and 386 at firstinput terminals IN1 to respectively receive the dynamically changedpower supply voltages VDD1-2 and VDD1-N. Each power path controller 324and 326 may output, as an output power supply voltage PPC2_OUT andPPCN_OUT, a higher one of the dynamically changed power supply voltageVDD1-2 and VDD1-N from the corresponding power source 384 and 386 andthe fixed power supply voltage VDD1-1 at an output terminal OUT suchthat the higher one of the dynamically changed power supply voltageVDD1-2 and VDD1-N and the fixed power supply voltage VDD1-1 is suppliedto the corresponding memory core MC2 and MCN. Accordingly, the operationstability of the memory cores MC1, MC2 and MCN may be ensured while thepower consumption of the SoC 300 may be reduced.

In other example embodiments, the one power source 382 of the powersources 382, 384 and 386 may supply a power supply voltage VDD1-1 thatis dynamically changed according to the operating condition of thecorresponding function circuit IP1 while a voltage level of the powersupply voltage VDD1-1 is maintained to be higher than or equal to thevoltage level of the minimum power supply voltage required by the memorycores MC1, MC2 and MCN, and the other power sources 384 and 386 of thepower sources 382, 384 and 386 may supply power supply voltages VDD1-2and VDD1-N that are dynamically changed according to operatingconditions of the corresponding function circuits IP2 and IPN.

For example, as illustrated in FIG. 6, the one power source 382 maygenerate the power supply voltage VDD1-1 of which the voltage level isdynamically changed while being maintained to be higher than or equal tothat of the minimum power supply voltage VMR, and the memory core MC1included in the function circuit IP1 corresponding to the one powersource 382 may directly receive the power supply voltage VDD1-1 of whichthe voltage level is dynamically changed while being maintained to behigher than or equal to that of the minimum power supply voltage VMRfrom the one power source 382. The power path controllers 324 and 326may be commonly coupled to the one power source 382 at the second inputterminals IN2 to receive the power supply voltage VDD1-1 of which thevoltage level is dynamically changed while being maintained to be higherthan or equal to that of the minimum power supply voltage VMR, and maybe respectively coupled to the other power sources 384 and 386 at thefirst input terminals IN1 to respectively receive the dynamicallychanged power supply voltages VDD1-2 and VDD1-N. Each power pathcontroller 324 and 326 may output, as the output power supply voltagePPC2_OUT and PPCN_OUT, a higher one of the dynamically changed powersupply voltage VDD1-2 and VDD1-N from the corresponding power source 384and 386 and the power supply voltage VDD1-1 of which the voltage levelis dynamically changed while being maintained to be higher than or equalto that of the minimum power supply voltage VMR at the output terminalOUT such that the higher one of the dynamically changed power supplyvoltage VDD1-2 and VDD1-N and the power supply voltage VDD1-1 of whichthe voltage level is dynamically changed while being maintained to behigher than or equal to that of the minimum power supply voltage VMR issupplied to the corresponding memory core MC2 and MCN. Accordingly, theoperation stability of the memory cores MC1, MC2 and MCN may be ensuredwhile the power consumption of the SoC 300 may be reduced.

As described above, in the SoC 300 according to the example embodiments,the function circuits IP1, IP2 and IPN may be supplied with the powersupply voltages VDD1-1, VDD1-2 and VDD1-N from the power sources 382,384 and 386, respectively, and one 382 of the power sources 382, 384 and386 generating the power supply voltage VDD1-1 higher than or equal tothe minimum power supply voltage required by the memory cores MC1, MC2and MCN may be shared, thereby reducing the number of the power sourcesin the PMIC 360, the number of the passive elements and the number ofthe power supply lines between the PMIC 360 and the SoC 300.

FIG. 7 is a block diagram illustrating a SoC according to exampleembodiments.

Referring to FIG. 7, a SoC 400 includes a plurality of function circuitsIP1, IPM, IPM+1 and IPN, and a plurality of power path controller 422,424, 426 and 428. The SoC 400 of FIG. 7 may have a similar configurationto a SoC 100 of FIG. 1, except that each second power source 490 and 492is shared by a corresponding power group 410 and 412.

The function circuits IP1, IPM, IPM+1 and IPN may be coupled to aplurality of first power sources 482, 484, 486 and 488 included in aPMIC 460, respectively. A plurality of logic circuits LU1, LUM, LUM+1and LUN respectively included in the function circuits IP1, IPM, IPM+1and IPN (or peripheral circuits included in the logic circuits LU1, LUM,LUM+1 and LUN) may be supplied with a plurality of first power supplyvoltages VDD1-1, VDD1-M, VDD1-M+1 and VDD1-N from the first powersources 482, 484, 486 and 488, respectively.

Each power group 410 and 412 of the SoC 400 may share a correspondingsecond power source 490 and 492 included in the PMIC 460. For example,power path controllers 422 and 424 corresponding to the functioncircuits IP1 and IPM belonging to a first power group 410 may berespectively coupled to the first power sources 482 and 484 at firstinput terminals IN1, may be commonly coupled to the corresponding secondpower source 490 at second input terminals 1N2, and may be respectivelycoupled to memory cores MC1 and MCM included in the function circuitsIP1 and IPM belonging to the first power group 410 at output terminalsOUT. Each memory core MC1 and MCM included in the function circuit IP1and IPM belonging to the first power group 410 may be selectivelysupplied, by the corresponding power path controller 422 and 424, withthe dynamically changed first power supply voltage VDD1-1 and VDD1-Mfrom the corresponding first power source 482 and 484 or a fixed secondpower supply voltage VDD2-1 from the corresponding second power source490.

Power path controllers 426 and 428 corresponding to the functioncircuits IPM+1 and IPN belonging to a second power group 412 may berespectively coupled to the first power sources 486 and 488 at firstinput terminals IN1, may be commonly coupled to the corresponding secondpower source 492 at second input terminals IN2, and may be respectivelycoupled to memory cores MCM+1 and MCN included in the function circuitsIPM+1 and IPN belonging to the second power group 412 at outputterminals OUT. Each memory core MCM+1 and MCN included in the functioncircuit IPM+1 and IPN belonging to the second power group 412 may beselectively supplied, by the corresponding power path controller 426 and428, with the dynamically changed first power supply voltage VDD1-M+1and VDD1-N from the corresponding first power source 486 and 488 or afixed second power supply voltage VDD2-2 from the corresponding secondpower source 492.

As described above, in the SoC 400 according to the example embodiments,each second power source 490 and 492 may be shared by the correspondingpower group 410 and 412, thereby reducing the number of the powersources in the PMIC 460, the number of the passive elements and thenumber of the power supply lines between the PMIC 460 and the SoC 400.

FIG. 8 is a block diagram illustrating a SoC according to exampleembodiments.

Referring to FIG. 8, a SoC 500 includes a plurality of function circuitsIP1, IP2 and IPN, a plurality of power path controller 522, 524 and 526,and a second power source 590. The SoC 500 of FIG. 8 may have a similarconfiguration to a SoC 100 of FIG. 1, except that the second powersource 590 is located inside the SoC 500.

The function circuits IP1, IP2 and IPN may be coupled to a plurality offirst power sources 582, 584 and 586 included in a PMIC 560,respectively. A plurality of logic circuits LU1, LU2 and LUNrespectively included in the function circuits IP1, IP2 and IPN (orperipheral circuits included in the logic circuits LU1, LU2 and LUN) maybe supplied with a plurality of first power supply voltages VDD1-1,VDD1-2 and VDD1-N from the first power sources 582, 584 and 586,respectively.

A plurality of power path controllers 522, 524 and 526 may berespectively coupled to the first power sources 582, 584 and 586included in the PMIC 560 located outside the SoC 500, may be commonlycoupled to the second power source 590 included in the SoC 500. Thesecond power source 590 may generate a second power supply voltage VDD2that is a fixed power supply voltage corresponding to the minimum powersupply voltage required by memory cores MC1, MC2 and MCN. In someexample embodiments, the second power source 590 may directly receive apower supply voltage from an external battery, and may convert the powersupply voltage into the second power supply voltage VDD2. In otherexample embodiments, the power supply voltage from the external batterymay be converted by a buck converter 595 included in the PMIC 560, andthen may be converted into the second power supply voltage VDD2 by thesecond power source 590.

Each memory core MC1, MC2 and MCN may be selectively supplied, by thecorresponding power path controller 522, 524 and 526, with thedynamically changed first power supply voltage VDD1-1, VDD1-2 and VDD1-Nfrom the corresponding first power source 582, 584 and 586 or a fixedsecond power supply voltage VDD2 from the second power source 590.Accordingly, the operation stability of the memory cores MC1, MC2 andMCN may be ensured while the power consumption of the SoC 500 may bereduced.

FIG. 9 is a block diagram illustrating a SoC according to exampleembodiments.

Referring to FIG. 9, a SoC 600 includes a plurality of function circuitsIP1, IP2 and IPN, a plurality of power path controller 622, 624 and 626,and one power source 682 for one function circuit IP1 of the functioncircuits IP1, IP2 and IPN. The SoC 600 of FIG. 9 may have a similarconfiguration to a SoC 300 of FIG. 4, except that the one power source682 is located inside the SoC 600.

The one function circuit IP1 of the function circuits IP1, IP2 and IPNmay be coupled to the power source 682 located inside the SoC 600, andthe other function circuits IP2 and IPN of the function circuits IP1,IP2 and IPN may be coupled to power sources 684 and 686 included in anexternal PMIC 660, respectively. A plurality of logic circuits LU1, LU2and LUN respectively included in the function circuits IP1, IP2 and IPN(or peripheral circuits included in the logic circuits LU1, LU2 and LUN)may be supplied with a plurality of power supply voltages VDD1-1, VDD1-2and VDD1-N from the power sources 682, 684 and 686, respectively.

The one power source 682 located inside the SoC 600 may supply a fixedpower supply voltage VDD1-1 corresponding to a minimum power supplyvoltage required by memory cores MC1, MC2 and MCN, or a power supplyvoltage VDD1-1 that is dynamically changed according to the operatingcondition of the corresponding function circuit IP1 while a voltagelevel of the power supply voltage VDD1-1 is maintained to be higher thanor equal to the voltage level of the minimum power supply voltage. Thepower sources 684 and 686 included in the PMIC 660 may supply powersupply voltages VDD1-2 and VDD1-N that are dynamically changed accordingto operating conditions of the corresponding function circuits IP2 andIPN.

The memory core MC1 included in the function circuit IP1 may directlyreceive the power supply voltage VDD1-1 from the power source 682located inside the SoC 600. The power path controllers 624 and 626 maybe commonly coupled to the power source 682 located inside the SoC 600,and may selectively transfer the power supply voltage VDD1-2 and VDD1-Nfrom the corresponding power source 684 and 686 included in the PMIC 660or the power supply voltage VDD1-1 from the power source 682 locatedinside the SoC 600 to the corresponding memory core MC2 and MCN.Accordingly, the operation stability of the memory cores MC1, MC2 andMCN may be ensured while the power consumption of the SoC 600 may bereduced.

FIG. 10 is a block diagram illustrating a mobile device according toexample embodiments, and FIG. 11 is a schematic diagram illustrating anexample in which the mobile device of FIG. 10 is implemented as asmart-phone.

Referring to FIGS. 10 and 11, a mobile device 700 (or an electronicdevice) includes a SoC 710 and a PMIC 780. In some example embodiments,the mobile device 700 may further include a plurality of devices ormodules 720, 730, 740, 750, 760 and 770, such as a memory device 720, astorage device 730, a communication module 740, a camera module 750, adisplay module 760, a touch panel module 770, etc. For example, asillustrated in FIG. 11, the mobile device 700 may be implemented as asmart-phone.

The SoC 710 may control overall operations of the mobile device 700. Forexample, the SoC 710 may control the memory device 720, the storagedevice 730 and the plurality of modules 740, 750, 760 and 770. In someexample embodiments, the SoC 710 may be an application processor (AP)included in the mobile device 700.

The SoC 710 may be one of the SoCs 100, 300, 400, 500 and 600illustrated in FIGS. 1, 4, 7, 8 and 9, respectively, and may be suppliedwith power from the PMIC 780. The SoC 710 may include a plurality offunction circuits IP1 and IPN and a plurality of power path controllersPPC1 and PPCN. A plurality of logic circuits LU1 and LUN included in thefunction circuits IP1 and IPN may be supplied with dynamically changedfirst power supply voltages from a plurality of first power sourcesPS1-1 and PS1-N included in the PMIC 780, respectively. The power pathcontrollers PPC1 and PPCN may be respectively coupled to the first powersources PS1-1 and PS1-N included in the PMIC 780, and may be commonlycoupled to at least one second power source PS2 included in the PMIC780. The second power source PS2 may generate a fixed second powersupply voltage. The power path controllers PPC1 and PPCN may selectivelyprovide the dynamically changed first power supply voltage from thecorresponding first power source PS1-1 and PS1-N or the fixed secondpower supply voltage from the second power source PS2 to correspondingmemory cores MC1 and MCN, respectively. Accordingly, the SoC 710according to the example embodiments may ensure a normal operation ofthe memory cores MC1 and MCN while reducing power consumption. Further,in the SoC 710 according to the example embodiments, the power pathcontrollers PPC1 and PPCN may share (or may be commonly coupled to) thesecond power source PS2, thereby reducing the number of power sources,the number of passive elements and the number of power supply lines.

The memory device 720 and the storage device 730 may store data foroperations of the mobile device 700. The memory device 720 may include avolatile memory device, such as a dynamic random access memory (DRAM), aSRAM, a mobile DRAM, etc. The storage device 730 may include anonvolatile memory device, such as an erasable programmable read-onlymemory (EPROM), an electrically erasable programmable read-only memory(EEPROM), a flash memory, a phase change random access memory (PRAM), aresistance random access memory (RRAM), a nano floating gate memory(NFGM), a polymer random access memory (PoRAM), a magnetic random accessmemory (MRAM), a ferroelectric random access memory (FRAM), etc. In someexample embodiments, the storage device 730 may further include a solidstate drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

The plurality of modules 740, 750, 760 and 770 may perform variousfunctions of the mobile device 700. For example, the mobile device 700may include the communication module 740 that performs a communicationfunction (e.g., a code division multiple access (CDMA) module, a longterm evolution (LTE) module, a radio frequency (RF) module, anultra-wideband (UWB) module, a wireless local area network (WLAN)module, a worldwide interoperability for a microwave access (WIMAX)module, etc.), the camera module 750 that performs a camera function,the display module 760 that performs a display function, the touch panelmodule 770 that performs a touch sensing function, etc. In some exampleembodiments, the mobile device 700 may further include a globalpositioning system (GPS) module, a microphone (MIC) module, a speakermodule, a gyroscope module, etc. However, the functional modules 740,750, 760, and 770 in the mobile device 700 are not limited thereto.

FIG. 12 is a block diagram illustrating an interface included in amobile device according to example embodiments.

Referring to FIG. 12, a mobile device 800 includes a SoC 802 and aplurality of interfaces 811, 812, 813, 814, 815, 816, 817, 818, 819,820, 821, 822 and 823. According to example embodiments, the mobiledevice 800 may be any mobile device, such as a mobile phone, a smartphone, a tablet computer, a laptop computer, a personal digitalassistants (PDA), a portable multimedia player (PMP), a digital camera,a portable game console, a music player, a camcorder, a video player, anavigation system, etc.

The SoC 802 controls overall operations of the mobile device 800. Forexample, the SoC 802 may be an application processor (AP) included inthe mobile device 800.

The SoC 802 may communicate with each of a plurality of peripheraldevices via each of the plurality of interfaces 811 through 823. Forexample, each of the interfaces 811 through 823 may transmit at leastone control signal, which is output from a corresponding one of aplurality of function circuits IP1 and IPN, to each of the plurality ofperipheral devices.

For example, the SoC 802 may control a power state and an operationstate of each flat panel display device via each of display interfaces811 and 812. The flat panel display device may include a liquid crystaldisplay (LCD), a light emitting diode (LED) display, an organic lightemitting diode (OLED) display or an active matrix organic light-emittingdiode (AMOLED) display, etc.

The SoC 802 may control a power state and an operation state of acamcorder via a camcorder interface 813, may control a power state andan operation state of a TV module via a TV interface 814, and maycontrol a power state and an operation state of a camera module or animage sensor module via an image sensor interface 815.

The SoC 802 may control a power state and an operation state of a GPSmodule via a GPS interface 816, may control a power state and anoperation state of a UWB module via a UWB interface 817, and may controla power state and an operation state of an universal serial bus (USB)drive via a USB drive interface 818.

The SoC 802 may control a power state and an operation state of a DRAMvia a DRAM interface 819, may control a power state and an operationstate of a nonvolatile memory device (e.g., a flash memory) via anonvolatile memory interface 820 (e.g., a flash memory interface), maycontrol a power state and an operation state of an audio module throughan audio interface 821, may control a power state of a multi-formatcodec (MFC) through an MFC interface 822, and may control a power stateof an MP3 player through an MP3 player interface 823. For example, amodule or an interface may be implemented in hardware or software.

The SoC 802 may be one of the SoCs 100, 300, 400, 500 and 600illustrated in FIGS. 1, 4, 7, 8 and 9, respectively. The SoC 802 mayinclude a plurality of function circuits IP1 and IPN and a plurality ofpower path controllers PPC1 and PPCN. A plurality of logic circuits LU1and LUN included in the function circuits IP1 and IPN may be suppliedwith dynamically changed first power supply voltages, respectively. Eachpower path controller PPC1 and PPCN may selectively provide thedynamically changed first power supply voltage or a fixed second powersupply voltage to a corresponding memory core MC1 and MCN. Accordingly,the SoC 802 according to the example embodiments may ensure a normaloperation of the memory cores MC1 and MCN while reducing powerconsumption. Further, in the SoC 802 according to the exampleembodiments, the power path controllers PPC1 and PPCN may share (or maybe commonly coupled to) the second power source, thereby reducing thenumber of power sources, the number of passive elements and the numberof power supply lines.

FIG. 13 is a block diagram illustrating an electronic device accordingto example embodiments.

Referring to FIG. 13, an electronic device 1000 includes an imageprocessing circuit 1100, a wireless transceiving circuit 1200, an audioprocessing circuit 1300, an image file generator 1400, a memory device1500, a user interface 1600, an application processor 1700 and a PMIC1800.

The image processing circuit 1100 may include a lens 1110, an imagesensor 1120, an image processor 1130 and a display 1140. The wirelesstransceiving circuit 1200 may include an antenna 1210, a transceiver1220 and a modem 1230. The audio processing circuit 1300 may include anaudio processor 1310, a microphone 1320 and a speaker 1330.

The application processor 1700 may be one of the SoCs 100, 300, 400, 500and 600 illustrated in FIGS. 1, 4, 7, 8 and 9, respectively. Theapplication processor 1700 may be supplied with a plurality of firstpower supply voltages respectively corresponding to a plurality offunction circuits or a plurality of power domains from the PMIC 1800,and the first power supply voltages may be dynamically changed to reducepower consumption of the application processor 1700. Further, theapplication processor 1700 may be supplied with a fixed second powersupply voltage corresponding to a minimum power supply voltage requiredby a plurality of memory cores included in the application processor1700 from the PMIC 1800. The application processor 1700 may selectivelyprovide the first power supply voltage or the second power supplyvoltage to each memory core by using a plurality of power pathcontrollers respectively corresponding to the plurality of memory cores,and thus may ensure the normal operation of the memory cores whilereducing the power consumption. Further, the application processor 1700may receive the second power supply voltage from a single or reducednumber of power sources, thereby reducing the number of power sources,the number of passive elements and the number of power supply lines.

At least one of the components, elements or units represented by a blockas illustrated in FIGS. 1, 3, 4 and 7-10 (e.g., power path controller122 in FIG. 1, switch controller 230 in FIG. 3) may be embodied asvarious numbers of hardware, software and/or firmware structures thatexecute respective functions described above, according to an exemplaryembodiment. For example, at least one of these components, elements orunits may use a direct circuit structure, such as a memory, processing,logic, a look-up table, etc. that may execute the respective functionsthrough controls of one or more microprocessors or other controlapparatuses. Also, at least one of these components, elements or unitsmay be specifically embodied by a module, a program, or a part of code,which contains one or more executable instructions for performingspecified logic functions. Also, at least one of these components,elements or units may further include a processor such as a CPU thatperforms the respective functions, a microprocessor, or the like. Two ormore of these components, elements or units may be combined into onesingle component, element or unit which performs all operations orfunctions of the combined two or more components, elements of units.Further, although a bus is not illustrated in the above block diagrams,communication between the components, elements or units may be performedthrough the bus. Functional aspects of the above exemplary embodimentsmay be implemented in algorithms that execute on one or more processors.Furthermore, the components, elements or units represented by a block orprocessing steps may employ any number of related art techniques forelectronics configuration, signal processing and/or control, dataprocessing and the like.

According to example embodiment, the functions or operations performedby the various components, elements or units in FIGS. 1, 3, 4 and 7-10may be embodied as computer readable codes on a computer readablerecording medium, or to be transmitted through a transmission medium.The computer readable recording medium is any data storage device thatcan store data which can be thereafter read by a computer system.Examples of the computer readable recording medium include read-onlymemory (ROM), RAM, CD-ROMs, magnetic tapes, floppy disks, and opticaldata storage devices. The transmission medium can include carrier wavestransmitted through the Internet or various types of communicationchannel. The computer readable recording medium can also be distributedover network coupled computer systems so that the computer readable codeis stored and executed in a distributed fashion.

According to example embodiments, there is provided a method ofcontrolling an SoC which may include the functions or operationsperformed by the various components, elements or units in FIGS. 1, 3, 4and 7-10. Since these functions and operations will be duplicate,detailed descriptions thereof are omitted.

The example embodiments disclosed herein may be used in various kinds ofSoCs or a system including the SoCs, such as a mobile phone, a smartphone, a PDA, a PMP, a digital camera, a digital television, a set-topbox, a music player, a portable game console, a navigation device, a PC,a server computer, a workstation, a tablet computer, a laptop computer,a smart card, a printer, etc.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Although a few example embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible to the example embodiments withoutmaterially departing from the novel teachings and advantages of theinventive concept. Accordingly, all such modifications are intended tobe included within the scope of the inventive concept as defined in theclaims. Therefore, it is to be understood that the foregoing isillustrative of various example embodiments and is not to be construedas limited to the specific example embodiments disclosed, and thatmodifications to the disclosed example embodiments, as well as otherexample embodiments, are intended to be included within the scope of theappended claims.

What is claimed is:
 1. A system-on-chip (SoC) comprising: a plurality of function circuits each of which comprises a logic circuit and a memory; and a plurality of power path controllers respectively coupled to a plurality of first power sources at first input terminals, commonly coupled to a second power source at second input terminals, and respectively coupled to the memories at output terminals, wherein the logic circuits are respectively coupled to the first power sources, and configured to be supplied with a plurality of first power supply voltages from the first power sources, respectively, and wherein each of the memories is configured to be selectively supplied, by a corresponding one of the power path controllers, with one of a corresponding one of the first power supply voltages from a corresponding one of the first power sources and a second power supply voltage from the second power source.
 2. The SoC of claim 1, wherein each of the first power supply voltages is a power supply voltage which is dynamically changed according to an operating condition of a corresponding one of the function circuits, and wherein the second power supply voltage is a fixed power supply voltage. 3-4. (canceled)
 5. The SoC of claim 1, wherein the power path controllers are respectively coupled to the first power sources through a plurality of first power supply lines, and are commonly coupled to the second power source through a single second power supply line.
 6. The SoC of claim 1, wherein each power path controller is configured to transfer the corresponding one of the first power supply voltages from the corresponding one of the first power sources to a corresponding one of the memories in response to the corresponding one of the first power supply voltages having a voltage level higher than a voltage level of the second power supply voltage, and transfer the second power supply voltage from the second power source to the corresponding one of the memories in response to the corresponding one of the first power supply voltages having a voltage level lower than the voltage level of the second power supply voltage.
 7. The SoC of claim 6, wherein each power path controller comprises: a first switch located between the corresponding one of the first power sources and the corresponding one of the memories; a second switch located between the second power source and the corresponding one of the memories; a comparator configured to compare the corresponding one of the first power supply voltages from the corresponding one of the first power sources with the second power supply voltage from the second power source; and a switch controller configured to activate the first switch in response to the corresponding one of the first power supply voltages having the voltage level higher than the voltage level of the second power supply voltage, and activate the second switch in response to the corresponding one of the first power supply voltages having the voltage level lower than the voltage level of the second power supply voltage.
 8. The SoC of claim 1, wherein the first power supply voltage supplied from one of the first power sources is a fixed power supply voltage, and the first power supply voltages supplied from the others of the first power sources are power supply voltages which are dynamically changed according to operating conditions of corresponding ones of the function circuits, and wherein the second input terminals of the power path controllers are commonly coupled to, as the second power source, the one of the first power sources supplying the fixed power supply voltage.
 9. The SoC of claim 1, wherein the first power sources are buck converters, and the second power source is a low dropout regulator.
 10. The SoC of claim 1, wherein the first power sources and the second power source are included in a power management integrated circuit.
 11. The SoC of claim 1, wherein the second power source is located inside the SoC.
 12. A system-on-chip (SoC) of claim 1 further comprising another function circuit comprising a logic circuit and a memory which are configured to be supplied with the second power voltage from the second power source.
 13. The SoC of claim 12, wherein each of the first power supply voltages is a power supply voltage which is dynamically changed according to an operating condition of a corresponding one of the function circuits, and wherein the second power supply voltage is a fixed power supply voltage.
 14. The SoC of claim 12, wherein each of the first power supply voltages is a power supply voltage which is dynamically changed according to an operating condition of a corresponding one of the function circuits, and wherein the second power supply voltage is dynamically changed according to an operating condition of the other function circuit.
 15. The SoC of claim 14, wherein the second power supply voltage is a voltage level higher than or equal to a voltage level of a minimum power supply voltage required by the memories respectively included in the function circuits and the memory included in the other function circuit.
 16. A system-on-chip (SoC) of claim 1, wherein the second power source is included in the SoC.
 17. The SoC of claim 16, wherein the second power source generates a fixed power supply voltage as the second power supply voltage.
 18. An electronic device, comprising: the SoC of claim 1; and a power management integrated circuit which is connected to the SoC and comprises: the plurality of first power sources configured to generate the first power supply voltages each of which is dynamically changed according to an operating condition of a corresponding one of the function circuits; and the second power source configured to generate a fixed second power supply voltage. 19-20. (canceled)
 21. A system-on-chip (SoC) comprising: a first function circuit comprising a logic circuit and a first memory; and a second function circuit comprising a second memory; wherein the logic circuit is configured to be supplied with a first voltage which is dynamically changed according to an operating condition of the first function circuit, wherein each of the first and second memories is configured to be selectively supplied with one of the first voltage and a second voltage which is the same as or higher than a minimum voltage required by the first and second memories, and wherein the second voltage is supplied from one single power source.
 22. The SoC of claim 21, wherein each of the first and second memories is configured to be supplied with one of the first and second voltages which is higher than the other.
 23. The SoC of claim 21, wherein the second voltage is a fixed voltage.
 24. The SoC of claim 21, wherein the second voltage is configured to be dynamically changed according to an operating condition of the second function circuit. 